asm = Some general RISC-V assembly language tools/docs
D1 = Allwinner D1 and D1s/F133 SoC specific
Rust = Risc-V+Rust
rvv = RISC-V Vector extension (mainly for 0.7.1 available on D1)

RISC-V specifications: https://riscv.org/technical/specifications/
extensions not in specifications book but ratified: https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions

* GNU toolchain supports both RV32 and RV64 and is available on most Linux Distributions

* Qemu support RV32 and RV64, but without display in 6.0, need to use console or remote display (ssh -X for X11, etc...) https://www.qemu.org/
* TinyEMU (RISC-V emulator by main author of Qemu): https://bellard.org/tinyemu/
* ESP32 RISC-V simulator: https://codeberg.org/vak/esp32-riscv-sim

C#/Mono/.NET nanoFramework: https://microhobby.com.br/blog/2021/12/28/running-dotnet-on-risc-v/
* Work on Espressif ESP32-C3, Kendryte K210, StarFive JH7100, Allwinner D1

Compiling Firefox on RISC-V64: https://wontfix.blogspot.com/2021/07/

FPGA:
I made a curated MarkDown file (could have some errors) about available RISC-V implementations for FPGA:
https://framagit.org/popolon/risc-v_and_fpga/