Synthesizing bitstream for Tang Nano 4K from verilog and upload it to the board (in BRAM). build_tangnano4k-12.sh is for yosys <=12, build_tangnano4k.sh is for yosys >=13
* build_tangnano4k-12.sh
* build_tangnano4k.sh

About Open Source FPGA development

See Verilog/ for Verilog specific informations.

Look at ArchLinuxX86/fpga/ (x86_64), ArchLinuxRISC-V/fpga/ (RISC-V64) and ArchLinuxARM/ (ARMv7 and some ARMv8:) for binaries packages

Headdquarter of opensource FPGA synthesis
https://yosyshq.net/ (based on Verilog-2005, lot of converters including OpenCL)

For VHDL: http://ghdl.free.fr/ with ghdl-yosys-plugin https://github.com/ghdl/ghdl-yosys-plugin/
: installation/usage: http://pepijndevos.nl/2019/08/15/open-source-formal-verification-in-vhdl.html

Building FPGA with schematic circuit:
https://icestudio.io/

Programmer/flasher OpenFPGALoader:
https://github.com/trabucayre/openFPGALoader

OpenOCD: https://openocd.org/

Silice, is an efficient  FPGA development language
https://github.com/sylefeb/Silice/

RISC-V
I made a curated MarkDown file (could have some errors) about available RISC-V implementations for FPGA:
https://framagit.org/popolon/risc-v_and_fpga/

Nice game tutorial to learn digital logic (used by FPGA) by drawing schematics:
https://sebastian.itch.io/digital-logic-sim

Repository of opensource cores usable with FPGA:
https://www.librecores.org/